1. Field of the Invention
The present invention relates to a metal-oxide-semiconductor (MOS) transistor, especially referred to an n-type metal-oxide-semiconductor (NMOS) transistor and the manufacturing method thereof.
2. Description of the Prior Art
MOS transistors are among most commonly used semiconductor components. MOS transistors include vertical double-diffused MOS (VDMOS) and laterally-diffused MOS (LDMOS). Because LDNMOS transistors have higher operation bandwidth, higher operation efficiency, and a flat structure that can be easily integrated with other integrated circuits, LDNMOS transistors are widely used in high voltage environment, such as in a CPU power supply, power management system, AC/DC converter and high power or high frequency power amplifier. The operation characteristics of LDNMOS transistors are similar to those of NMOS transistors. The difference between them is that the N-drift region of an NMOS transistor is highly doped while the N-drift region of an LDNMOS transistor is lowly doped. This makes the N-drift region of the LDNMOS bear most voltage drop between the drain and gate, reducing the high electric field between the drain and gate, and resulting in a high breakdown voltage of the LDNMOS transistor.
Please refer to FIG. 1, FIG. 1 shows a prior art open drain circuit 100. As depicted in FIG. 1, an internal circuit 10 in the open drain circuit 100 is connected to an output driving element 11. The electro-discharge effect usually occurs at the input contact 15, output contact 16, high voltage contact 13 and low voltage contact 14. To prevent the output driving element 11 from electro-discharge damage, the ESD clamp 12 is added to protect the open drain element 11. Because the trigger voltage of the ESD clamp 12 is usually lower than that of the output driving element 11, the electro-discharge current will pass through the ESD clamp 12 rather than the output driving element 11.
The ESD clamp 12 is usually made of NMOS transistors. The low trigger voltage of the NMOS transistor allows the NMOS transistor to discharge more quickly thereby demonstrating a high performance of the ESD clamp 12 to protect the open drain element 11. A typical approach to further improve the performance of the ESD clamp 12 is to reduce the channel length of the NMOS transistor so as to reduce the breakdown voltage of the NMOS transistor. However, reducing the channel length of the NMOS transistor will cause the NMOS transistor to leak current, reducing the reliability of the NMOS transistor.